Embodiments of the present invention relate to processing data, and more particularly to processing data in a processor pipeline.
Instructions executed in a pipelined manner within a processor such as a microprocessor can have different latencies, as different instructions may require different cycles to complete. As an example, multiply-accumulate or divide operations may be pipelined into multiple execution paths of an execute stage for purposes of power and timing convergence. These instructions consume different amounts of cycles to execute, and thus have varying latencies.
In processor pipelines that support instructions of varying latencies, resource hazards may occur. A resource hazard occurs when multiple instructions or data thereof seek to use the same resource within a single cycle. Most architectures handle resource hazards by disallowing their occurrence by labeling the hazards as illegal. Such restrictions place a burden on software, including a compiler or assembler, and/or a programmer developing code. Additional overhead may be consumed and performance affected by requiring modifications to assembly code to overcome such resource hazards.
A stall is another event that can impact processor performance. Stalls occur when a pipeline stage signals to other stages to stop executing for one or more cycles so that the stage requesting the stall can “catch up”. Such stalls negatively impact performance.
A need thus exists to more efficiently handle instructions of varying latencies and to reduce resource hazards and stalls, particularly in light of non-uniform pipeline latencies.